Configurable System-on-Chip Card: SoC/Card S1
The SoC/Card S1 provides a field-programmable SoC (System-on-Chip) with a high-performance "turbo" 8032 microcontroller (10 MIPS at 40 MHz), 2.048 configurable logic cells and 118 configurable I/O signals. The SoC/Card S1 also provides FLASH, SRAM, EEPROM memory for firmware and configuration data and a CAN field bus interface for industrial network integration. The SoC/Card S1 offers standard credit card footprint and two 64-pin stackthrough connectors with 2.54mm centers.
The SoC/Card S1 is based on a revolutionary new architecture in embedded system technologie: The Triscend CSoC (Configurable System-on-Chip) TE520, a member of the Triscend E5 familiy of Configurable System-on-Chip devices. The members of this family combines a high-performance industry standard 8032 microcontroller, complex programmable logic, RAM, a high-speed bus and many other functions onto a single chip.
One other part of this new architecture is FastChip, the Configurable System-on-Chip Development System. A main feature of FastChip is a soft module library with user- parameterizable IP blocks for serial communication, logic functions, memory, display drivers, control, I/O and many other functions. FastChip also includes the 8032 ASM and C initialization code for any member of the soft module library.
The FastChip software manages the entire SoC/Card S1 CSoC design process - from configuring the on-board CSoC TE520 programmable logic to system level debugging over a JTAG-based serial link between the development system and the SoC/Card S1. To speed design development, FastChip provides seamless integration with 3rd party microprocessor and EDA tools. The members of the FastChip soft module library of user- parameterizable soft logic modules can be included in the SoC/Card S1 CSoC TE520 programmable logic by simply "dragging and dropping". FastChip also provides in-system programmable (ISP) capability and system-level real-time debugging.
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The SoC/Card S1 is build around the Triscend Configurable System-on-Chip (CSoC) TE520. This CSoC provides a 40 MHz Turbo 8032 MCU with 10 MIPS, some peripheral blocks with DMA, Address Mappers, Memory Interface Unit and other. The TE520 also provides programmable logic with 2.048 logic cells called "Configurable System Logic (CSL)" and a internal bus system with the name "Configurable System Interconnect (CSI) Bus". This bus links all parts within the TE520 together.
The external main components around the CSoC TE520 on the SoC/Card S1 are one FLASH chip with 256 KByte for 8032 programs and CSL configuration data, one 512 KByte SRAM, a SPI bus EEPROM for user setup data and one Microchip CAN controller MCP2510 with SPI interface. The FLASH and the SRAM interface to the TE520 is using the TE520-internal Memory Interface Unit. The interface for the SPI EEPROM and the CAN controller are based on the CSoC TE520 CSL and the PIO pins.
For system integration the SoC/Card S1 offers two 64-pin stackthrough connectors with two rows, each with 32-pins and 2.54mm centers. There are 128 pins in total. 8 of this 128 pins are used for power supply (four pins for GND, four other pins for +5VDC). 118 pins are direct connected to the CSoC TE520 CSL (Configurable System Logic). The function of this pins are configurable. Two other pins are used for the CAN field bus interface.
The SoC/Card S1 also offers a 16-pin connector with a JTAG interface. This interface is compatible with the IEEE standard 1149.1 for boundary-scan testing, permitting easy TE520 chip and SoC/Card S1 board-level testing. The SoC/Card S1 JTAG interface is also used for in-system programming and system-level real-time debugging together with the FastChip Configurable System-on-Chip Development System.