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Using the DIL/NetPC DNP/1486-3V PIO

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The DIL/NetPC DNP/1486-3V 20-bit general purpose parallel I/O (PIO) signals are based on 20 I/O pins of the AMD Elan SC410 32-bit microcontroller. The following table shows the details. For more information about the AMD Elan SC410 32-bit microcontroller please use the AMD SC400/SC410 literature.

The access to the DIL/NetPC DNP/1486-3V 20-bit general purpose parallel I/O signals is going over six AMD Elan SC410 special functions registers. There are two registers for each port, one mode register (PxMR) and one data register (PxDR). With the mode register, the input or output mode is set for each PIO bit. Over the data register, you can read the current of a input bit or write to a output bit.

The six mode and data registers are index registers within the AMD Elan SC410 chip setup and control (CSC) register space. These registers are indirectly accessible to the programmer by using a Chip Setup and Control Index Register (CSCIR) and a Chip Setup and Control Data Register (CSCDR).

All registers within the AMD Elan SC410 chip setup and control (CSC) register space are accessed through a mechanism called "indexed". This mechanism uses direct- mapped I/O index and data registers to expand the I/O space for reading and writing internal system registers. The access to the mode and data registers are illustrated in the following picture.

The picture shows the example of writing the value FFh to the CSC index A9h. All the AMD Elan SC410 chip setup and control (CSC) registers are accessed using a two-step process:

Within a program make sure that no interrupt occurs after the first I/O write. If the interrupt handler changes the content of the Chip Setup and Control Index Register (CSCIR) at I/O address 22h, the second I/O access after return from the interrupt uses not the correct register. Disable all interrupts before the first I/O write and enable the interrupts after the second I/O read or write. Use allways the following code fragment:

   	disable ();                // Disable Interrupts		
   	outportb (0x22, ....);	   // Set IndexPointer to ....
   	outportb (0x23, ....);	   // Read or Write Data from/to .... here
   	enable ();                 // Enable Interrupts  

The following C source code is a simple example for using the DNP/1486-3V 20-bit general purpose parallel I/O (PIO) signals on the DIL/NetPC evaluation board DNP/EVA1. On this evaluation board, the PIO Port A of the DNP/1486-3V is connected to 8 LEDīs and PIO Port B to a 8-position DIP switch.

It is necessary within this sample to set the bits for Port A as output and for Port B as input. After this setup, to turn a LED on, write a 1 to a Port A bit. If a DIP switch position on, you read a 1. The sample program first perform the setup operation. Then, the program reads in a loop the current state of the DIP switch on Port B and shows this state over the LEDīs on Port A.

// DIP-Switch Read Demo for DIL/NetPC DNP/1486-3V
// Written by KDW - 12.Mar.2000

#include ‹stdio.h›
#include ‹stdlib.h›
#include ‹conio.h›
#include ‹dos.h›

#define  CSCIR 0x22             // Chip Setup and Control Index Register
#define  CSCDR 0x23             // Chip Setup and Control Data Register
#define  PAMR  0xa5             // PIO Port A Mode Register
#define  PADR  0xa9             // PIO Port A Data Register
#define  PBMR  0xa4             // PIO Port B Mode Register
#define  PBDR  0xa8             // PIO Port B Data Register

void main (void) {
   int iDIPsw, iDIPswMirror;

   // Set SC410 for DIL/NetPC PIO Port A = Output

   disable ();
   outportb (CSCIR, PAMR);	   // Set IndexPointer to IndexRegister A5h
   outportb (CSCDR, 0xff);	   // IndexRegister A5h= 0xff (Output)

   // Set SC410 for DIL/NetPC PIO Port B = Input

   outportb (CSCIR, PBMR);         // Set IndexPointer to IndexRegister A4h
   outportb (CSCDR, 0x00);         // IndexRegister A4h= 0x00 (Input)

   // Build DIP-Switch Status Mirror

   outportb (CSCIR, PBDR);	   // Set IndexPointer to IndexRegister A8h
   iDIPswMirror= inportb (CSCDR);  // Read IndexRegister A8h
   enable ();

   // Show current DIP-Switch Status (Message and LEDīs)...

   printf ("\n  DIP-Switch= 0x%02x", iDIPswMirror & 0xff);
   disable ();
   outportb (CSCIR, PADR);
   outportb (CSCDR, iDIPswMirror & 0xff);
   enable ();

   // Read DIP-Switch and show Status until User Break...

   while (kbhit () == 0) {

      // Read current DIP-Switch Status.

      disable ();
      outportb (CSCIR, PBDR);		// Set IndexPointer to IndexRegister A8h
      iDIPsw= inportb (CSCDR);          // Read IndexRegister A8h
      enable ();

      // Compare current Status with last Status

      if (iDIPsw != iDIPswMirror) {

         // DIP-Switch Status change...

	 iDIPswMirror= iDIPsw;
	 printf ("\b\b%02x", iDIPsw & 0xff);	// Update Message
	 disable ();
	 outportb (CSCIR, PADR);                // Update LEDīs
	 outportb (CSCDR, iDIPsw & 0xff);
	 enable ();
      }
   }
   printf ("\n");
}

disable ()

enable ()

inportb ()

outportb ()

It is to be considered, however, that the DIL/NetPC DNP/1486-3V is a 3.3 volt- based system. The output levels of the parallel I/O signals are derived from the 3.3 volt supply voltage. If these signals are inputs, not all inputs can be driven by external 5 volt components. The following table shows more details.